1. Field
The present disclosure relates generally to optimizing the transfer of packets in a resource constrained operating environment.
2. Background
Many electronic devices employ a central processing unit (CPU) to perform highly sophisticated and complex processing functions. An ARM (Advanced RISC Machine) processor is just one example of a CPU that is widely used today for mobile applications because of its efficient, low-power architecture. The CPU generally operates with system memory, which holds the software programs and data needed by the CPU to perform its functions.
Direct memory access (DMA) is a common feature that allows certain hardware subsystems within the electronic device to access system memory independently of the CPU. This is typically achieved with a DMA command issued by the CPU, which enables the DMA to copy a block of data from system memory to a buffer within the hardware subsystem, or vice versa. Because the DMA is executing the data transfer, the CPU is available to perform other operations while the transfer is in progress.
Although DMA has proven to be a useful feature, there are a number of disadvantages. The use of a memory in the hardware subsystem solely for buffering is expensive. This is especially true in packet-based communication devices where the quality of service (QoS) requirements may necessitate the buffering of the entire packet at numerous stages throughout the hardware subsystem. In such cases it may not be possible to reuse the same buffer memory for multiple hardware stages. In cases where the communication device is placed in an idle or disabled state for a specific period of time or a specific usage mode, it may not be possible to reuse the memory elsewhere in the device to enhance overall system capability or performance. In addition, the power consumed by a DMA transfer is undesirable in ultra-low power applications, such as those typically encountered in short range wireless communications.